1. Field of the Invention
The invention relates generally to a device for detecting the level of a supply voltage supplied from the outside, and more particularly to, a supply voltage level detector for detecting the difference in the reference voltage and a compare voltage to detect the voltage of a desired level.
2. Description of the Prior Art
Generally, semiconductor devices are comprised of various types of circuits. A supply voltage supplied from the outside drives each of the circuits. However, as erroneous operation of the circuit can be generated if the level of the supply voltage is changed to exceed the range of an operating voltage of each of the circuits, it is required that the circuit be normally operated within a voltage range of an adequate level by sensing the level of the supply voltage. For example, in case of a clamping circuit or a boosting circuit for applying a proper bias voltage to word lines in a memory device, it is required that a voltage within an adequate range be outputted by sensing variations in the supply voltage since the output voltage is varied depending on the supply voltage. In order to detect the level of the supply voltage, a supply voltage level detector is used.
As shown in FIG. 1, the supply voltage level detector includes a reference voltage generator 1 for generating a reference voltage Vref of a constant level depending on a control signal ctrlb, a compare voltage generator 2 for generating a compare voltage afvdd/hfvdd the variation ratio of which is greater than the supply voltage VDD supplied from the outside depending on a control signal ctrlb, and a comparator 3 for comparing the reference voltage Vref and the compare voltage afvdd/hfvdd depending on the control signal ctrlb to output a signal vdd_det of a HIGH state if the supply voltage VDD is higher than a given level and to output a signal vdd_det of a LOW state if the supply voltage VDD is lower than a given level.
However, in the conventional supply voltage level detector, the variation in the voltage afvdd outputted from the compare voltage generator 2 is smaller than the variation in the supply voltage VDD, as shown in FIG. 6. Therefore, there are problems that not only the detection speed is low but also the sensing margin is reduced by a noise.
In other words, the conventional compare voltage generator 2 is constructed to output the voltage hfvdd distributed by resistors R1 and R2 if a PMOS transistor P1 is turned on by the control signal ctrlb, as shown in FIG. 2, the difference in the reference voltage Vref and the compare voltage hfvdd is small as shown in FIG. 6, and the output of the comparator 3 is thus delayed so that an erroneous operation can be caused by a little noise.
The present invention is contrived to solve the above problems and an object of the present invention is to provide a supply voltage level detector in which a compare voltage generator is constructed so that the variations in a compare voltage becomes great depending on a supply voltage.
In order to accomplish the above object, a supply voltage level detector according to the present invention, is characterized in that it comprises a reference voltage generator for generating the reference voltage of a constant level depending on a control signal; a compare voltage generator for generating a compare voltage the variation ratio of which is higher than the supply voltage supplied from the outside depending on the control signal; and a comparator for comparing the reference voltage and the compare voltage depending on the control signal to output a given signal, wherein the compare voltage generator comprises, a first PMOS transistor driven by the control signal, a source of which being connected to the supply voltage; a resistor connected between a drain of the first PMOS transistor and a node; a second PMOS transistor connected between the supply voltage and an output terminal and driven by the control signal; and a NMOS transistor connected between the output terminal and the ground, a gate of which being connected to the node.
The NMOS transistor is formed in a substrate having a well of a triple structure, wherein a P well is connected to the node, an N well is connected to the supply voltage and the substrate is connected to the ground.
Also, a supply voltage level detector according to the present invention, is characterized in that it comprises a reference voltage generator for generating the reference voltage of a constant level depending on a control signal; a compare voltage generator for generating a compare voltage the variation ratio of which is higher than the supply voltage supplied from the outside depending on the control signal; and a comparator for comparing the reference voltage and the compare voltage depending on the control signal to output a given signal, wherein the compare voltage generator comprises, a first PMOS transistor driven by the control signal, a source of which being connected to the supply voltage; a resistor connected between a drain of the first PMOS transistor and a node; a diode connected between said node and a ground; a second PMOS transistor connected between the supply voltage and an output terminal and driven by the control signal; and a NMOS transistor connected between the output terminal and the ground, a gate of which being connected to the node.